The Resource A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof, by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul, (electronic resource)

A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof, by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul, (electronic resource)

Label
A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof
Title
A Pipelined Multi-core MIPS Machine
Title remainder
Hardware Implementation and Correctness Proof
Statement of responsibility
by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
Creator
Contributor
Author
Provider
Subject
Language
eng
Summary
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work
Member of
http://library.link/vocab/creatorName
Kovalev, Mikhail
Image bit depth
0
LC call number
QA76.9.A43
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Müller, Silvia M.
  • Paul, Wolfgang J.
  • SpringerLink
Series statement
Lecture Notes in Computer Science,
Series volume
9000
http://library.link/vocab/subjectName
  • Computer science
  • Computer hardware
  • Computer Communication Networks
  • Software engineering
  • Computer software
  • Computer Science
  • Algorithm Analysis and Problem Complexity
  • Software Engineering
  • Computer Hardware
  • Processor Architectures
  • Computer Communication Networks
  • Programming Languages, Compilers, Interpreters
Label
A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof, by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Dimensions
unknown
Extent
XII, 352 p. 147 illus.
File format
multiple file formats
Form of item
electronic
Isbn
9783319139067
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-319-13906-7
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-319-13906-7
Label
A Pipelined Multi-core MIPS Machine : Hardware Implementation and Correctness Proof, by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Dimensions
unknown
Extent
XII, 352 p. 147 illus.
File format
multiple file formats
Form of item
electronic
Isbn
9783319139067
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-319-13906-7
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-319-13906-7

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