The Resource ASIC and FPGA verification : a guide to component modeling, Richard Munden, (electronic resource)

ASIC and FPGA verification : a guide to component modeling, Richard Munden, (electronic resource)

Label
ASIC and FPGA verification : a guide to component modeling
Title
ASIC and FPGA verification
Title remainder
a guide to component modeling
Statement of responsibility
Richard Munden
Creator
Subject
Genre
Language
  • eng
  • eng
Summary
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.<br
Member of
Cataloging source
MiAaPQ
http://library.link/vocab/creatorName
Munden, Richard
Dewey number
  • 621.3815
  • 621.395
Index
no index present
Language note
English
LC call number
TK7874.6
LC item number
.M86 2005
Literary form
non fiction
Nature of contents
dictionaries
Series statement
Systems on Silicon
http://library.link/vocab/subjectName
  • Application-specific integrated circuits
  • Integrated circuits
Label
ASIC and FPGA verification : a guide to component modeling, Richard Munden, (electronic resource)
Instantiates
Publication
Note
Description based upon print version of record
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
  • Front cover; ABOUT THE AUTHOR; Title page; Copyright Page; Table of Contents; PREFACE; Historical Background; Verilog, VHDL, and the Origin of VITAL; The VITAL Specification; The Free Model Foundry; Structure of the Book; Intended Audience; Resources for Help and Information; Acknowledgments; PART I INTRODUCTION; CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION; 1.1 Why Models Are Needed; 1.1.1 Prototyping; 1.1.2 Simulation; 1.2 Definition of a Model; 1.2.1 Levels of Abstraction; 1.2.2 Model Types; 1.2.3 Technology-Independent Models; 1.3 Design Methods and Models
  • 1.4 How Models Fit in the FPGA/ASIC Design Flow1.4.1 The Design/Verification Flow; 1.5 Where to Get Models; 1.6 Summary; CHAPTER 2 TOUR OF A SIMPLE MODEL; 2.1 Formatting; 2.2 Standard Interfaces; 2.3 Model Delays; 2.4 VITAL Additions; 2.4.1 VITAL Delay Types; 2.4.2 VITAL Attributes; 2.4.3 VITAL Primitive Call; 2.4.4 VITAL Processes; 2.4.5 VitalPathDelays; 2.5 Interconnect Delays; 2.6 Finishing Touches; 2.7 Summary; PART II RESOURCES AND STANDARDS; CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS; 3.1 STD_LOGIC_1164; 3.1.1 Type Declarations; 3.1.2 Functions; 3.2 VITAL_Timing; 3.2.1 Declarations
  • 3.2.2 Procedures3.3 VITAL_Primitives; 3.3.1 Declarations; 3.3.2 Functions and Procedures; 3.4 VITAL_Memory; 3.4.1 Memory Functionality; 3.4.2 Memory Timing Specification; 3.4.3 Memory Timing Checks; 3.5 FMF Packages; 3.5.1 FMF gen_utils and ecl_utils; 3.5.2 FMF ff_package; 3.5.3 FMF Conversions; 3.6 Summary; CHAPTER 4 AN INTRODUCTION TO SDF; 4.1 Overview of an SDF File; 4.1.1 Header; 4.1.2 Cell; 4.1.3 Timing Specifications; 4.2 SDF Capabilities; 4.2.1 Circuit Delays; 4.2.2 Timing Checks; 4.3 Summary; CHAPTER 5 ANATOMY OF A VITAL MODEL; 5.1 Level 0 Guidelines; 5.1.1 Backannotation
  • 5.1.2 Timing Generics5.1.3 VitalDelayTypes; 5.2 Level 1 Guidelines; 5.2.1 Wire Delay Block; 5.2.2 Negative Constraint Block; 5.2.3 Processes; 5.2.4 VITAL Primitives; 5.2.5 Concurrent Procedure Section; 5.3 Summary; CHAPTER 6 MODELING DELAYS; 6.1 Delay Types and Glitches; 6.1.1 Transport and Inertial Delays; 6.1.2 Glitches; 6.2 Distributed Delays; 6.3 Pin-to-Pin Delays; 6.4 Path Delay Procedures; 6.5 Using VPDs; 6.6 Generates and VPDs; 6.7 Device Delays; 6.8 Backannotating Path Delays; 6.9 Interconnect Delays; 6.10 Summary; CHAPTER 7 VITAL TABLES; 7.1 Advantages of Truth and State Tables
  • 7.2 Truth Tables7.2.1 Truth Table Construction; 7.2.2 VITAL Table Symbols; 7.2.3 Truth Table Usage; 7.3 State Tables; 7.3.1 State Table Symbols; 7.3.2 State Table Construction; 7.3.3 State Table Usage; 7.3.4 State Table Algorithm; 7.4 Reducing Pessimism; 7.5 Memory Tables; 7.5.1 Memory Table Symbols; 7.5.2 Memory Table Construction; 7.5.3 Memory Table Usage; 7.6 Summary; CHAPTER 8 TIMING CONSTRAINTS; 8.1 The Purpose of Timing Constraint Checks; 8.2 Using Timing Constraint Checks in VITAL Models; 8.2.1 Setup/Hold Checks; 8.2.2 Period/Pulsewidth Checks; 8.2.3 Recovery/Removal Checks
  • 8.2.4 Skew Checks
Dimensions
unknown
Extent
1 online resource (337 p.)
Form of item
online
Isbn
9781281008282
Media category
computer
Media type code
c
Specific material designation
remote
System control number
  • (EBL)226767
  • (OCoLC)437144741
  • (SSID)ssj0000073697
  • (PQKBManifestationID)11115769
  • (PQKBTitleCode)TC0000073697
  • (PQKBWorkID)10104355
  • (PQKB)10086912
  • (MiAaPQ)EBC226767
  • (EXLCZ)991000000000363782
Label
ASIC and FPGA verification : a guide to component modeling, Richard Munden, (electronic resource)
Publication
Note
Description based upon print version of record
Carrier category
online resource
Carrier category code
cr
Content category
text
Content type code
txt
Contents
  • Front cover; ABOUT THE AUTHOR; Title page; Copyright Page; Table of Contents; PREFACE; Historical Background; Verilog, VHDL, and the Origin of VITAL; The VITAL Specification; The Free Model Foundry; Structure of the Book; Intended Audience; Resources for Help and Information; Acknowledgments; PART I INTRODUCTION; CHAPTER 1 INTRODUCTION TO BOARD-LEVEL VERIFICATION; 1.1 Why Models Are Needed; 1.1.1 Prototyping; 1.1.2 Simulation; 1.2 Definition of a Model; 1.2.1 Levels of Abstraction; 1.2.2 Model Types; 1.2.3 Technology-Independent Models; 1.3 Design Methods and Models
  • 1.4 How Models Fit in the FPGA/ASIC Design Flow1.4.1 The Design/Verification Flow; 1.5 Where to Get Models; 1.6 Summary; CHAPTER 2 TOUR OF A SIMPLE MODEL; 2.1 Formatting; 2.2 Standard Interfaces; 2.3 Model Delays; 2.4 VITAL Additions; 2.4.1 VITAL Delay Types; 2.4.2 VITAL Attributes; 2.4.3 VITAL Primitive Call; 2.4.4 VITAL Processes; 2.4.5 VitalPathDelays; 2.5 Interconnect Delays; 2.6 Finishing Touches; 2.7 Summary; PART II RESOURCES AND STANDARDS; CHAPTER 3 VHDL PACKAGES FOR COMPONENT MODELS; 3.1 STD_LOGIC_1164; 3.1.1 Type Declarations; 3.1.2 Functions; 3.2 VITAL_Timing; 3.2.1 Declarations
  • 3.2.2 Procedures3.3 VITAL_Primitives; 3.3.1 Declarations; 3.3.2 Functions and Procedures; 3.4 VITAL_Memory; 3.4.1 Memory Functionality; 3.4.2 Memory Timing Specification; 3.4.3 Memory Timing Checks; 3.5 FMF Packages; 3.5.1 FMF gen_utils and ecl_utils; 3.5.2 FMF ff_package; 3.5.3 FMF Conversions; 3.6 Summary; CHAPTER 4 AN INTRODUCTION TO SDF; 4.1 Overview of an SDF File; 4.1.1 Header; 4.1.2 Cell; 4.1.3 Timing Specifications; 4.2 SDF Capabilities; 4.2.1 Circuit Delays; 4.2.2 Timing Checks; 4.3 Summary; CHAPTER 5 ANATOMY OF A VITAL MODEL; 5.1 Level 0 Guidelines; 5.1.1 Backannotation
  • 5.1.2 Timing Generics5.1.3 VitalDelayTypes; 5.2 Level 1 Guidelines; 5.2.1 Wire Delay Block; 5.2.2 Negative Constraint Block; 5.2.3 Processes; 5.2.4 VITAL Primitives; 5.2.5 Concurrent Procedure Section; 5.3 Summary; CHAPTER 6 MODELING DELAYS; 6.1 Delay Types and Glitches; 6.1.1 Transport and Inertial Delays; 6.1.2 Glitches; 6.2 Distributed Delays; 6.3 Pin-to-Pin Delays; 6.4 Path Delay Procedures; 6.5 Using VPDs; 6.6 Generates and VPDs; 6.7 Device Delays; 6.8 Backannotating Path Delays; 6.9 Interconnect Delays; 6.10 Summary; CHAPTER 7 VITAL TABLES; 7.1 Advantages of Truth and State Tables
  • 7.2 Truth Tables7.2.1 Truth Table Construction; 7.2.2 VITAL Table Symbols; 7.2.3 Truth Table Usage; 7.3 State Tables; 7.3.1 State Table Symbols; 7.3.2 State Table Construction; 7.3.3 State Table Usage; 7.3.4 State Table Algorithm; 7.4 Reducing Pessimism; 7.5 Memory Tables; 7.5.1 Memory Table Symbols; 7.5.2 Memory Table Construction; 7.5.3 Memory Table Usage; 7.6 Summary; CHAPTER 8 TIMING CONSTRAINTS; 8.1 The Purpose of Timing Constraint Checks; 8.2 Using Timing Constraint Checks in VITAL Models; 8.2.1 Setup/Hold Checks; 8.2.2 Period/Pulsewidth Checks; 8.2.3 Recovery/Removal Checks
  • 8.2.4 Skew Checks
Dimensions
unknown
Extent
1 online resource (337 p.)
Form of item
online
Isbn
9781281008282
Media category
computer
Media type code
c
Specific material designation
remote
System control number
  • (EBL)226767
  • (OCoLC)437144741
  • (SSID)ssj0000073697
  • (PQKBManifestationID)11115769
  • (PQKBTitleCode)TC0000073697
  • (PQKBWorkID)10104355
  • (PQKB)10086912
  • (MiAaPQ)EBC226767
  • (EXLCZ)991000000000363782

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