The Resource Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, by Vaibbhav Taraate, (electronic resource)

Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, by Vaibbhav Taraate, (electronic resource)

Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog
Title
Advanced HDL Synthesis and SOC Prototyping
Title remainder
RTL Design Using Verilog
Statement of responsibility
by Vaibbhav Taraate
Creator
Contributor
Author
Author
Provider
Subject
Language
eng
Summary
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike
http://library.link/vocab/creatorName
Taraate, Vaibbhav
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsaut
1Ana9qXmW6E
Image bit depth
0
LC call number
TK7888.4
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
SpringerLink
http://library.link/vocab/subjectName
  • Systems engineering
  • Microprogramming
  • Logic design
  • Circuits and Systems
  • Control Structures and Microprogramming
  • Logic Design
Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, by Vaibbhav Taraate, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level
Dimensions
unknown
Extent
XXI, 307 p. 263 illus., 196 illus. in color.
File format
multiple file formats
Form of item
electronic
Isbn
9789811087769
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-981-10-8776-9
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-981-10-8776-9
Label
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog, by Vaibbhav Taraate, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level
Dimensions
unknown
Extent
XXI, 307 p. 263 illus., 196 illus. in color.
File format
multiple file formats
Form of item
electronic
Isbn
9789811087769
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-981-10-8776-9
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-981-10-8776-9

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