Coverart for item
The Resource Advances in Computer Systems Architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings, edited by Lynn Choi, Yunheung Paek, Sangyeun Cho, (electronic resource)

Advances in Computer Systems Architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings, edited by Lynn Choi, Yunheung Paek, Sangyeun Cho, (electronic resource)

Label
Advances in Computer Systems Architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings
Title
Advances in Computer Systems Architecture
Title remainder
12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings
Statement of responsibility
edited by Lynn Choi, Yunheung Paek, Sangyeun Cho
Creator
Contributor
Editor
Provider
Subject
Language
eng
Summary
This book constitutes the refereed proceedings of the 12th Asia-Pacific Computer Systems Architecture Conference, ACSAC 2007, held in Seoul, Korea in August 2007. The 26 revised full papers presented together with 2 keynote 8 invited lectures were carefully reviewed and selected from 92 submissions. The papers encompass a wide range of topics, with much emphasis in hardware and software techniques for state-of-the-art multicore and multithreaded architectures
Member of
http://library.link/vocab/creatorName
Choi, Lynn
Image bit depth
0
LC call number
QA76.9.C62
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Paek, Yunheung.
  • Cho, Sangyeun.
  • SpringerLink
Series statement
Lecture Notes in Computer Science,
Series volume
4697
http://library.link/vocab/subjectName
  • Computer science
  • Data transmission systems
  • Logic design
  • Computer Communication Networks
  • Operating systems (Computers)
  • Computer Science
  • Arithmetic and Logic Structures
  • Input/Output and Data Communications
  • Logic Design
  • Computer Communication Networks
  • Processor Architectures
  • Operating Systems
Label
Advances in Computer Systems Architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings, edited by Lynn Choi, Yunheung Paek, Sangyeun Cho, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
A Compiler Framework for Supporting Speculative Multicore Processors -- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence -- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System -- Unbiased Branches: An Open Problem -- An Online Profile Guided Optimization Approach for Speculative Parallel Threading -- Entropy-Based Profile Characterization and Classification for Automatic Profile Management -- Laplace Transformation on the FT64 Stream Processor -- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation -- Evolution of NAND Flash Memory Interface -- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs -- Exploiting Single-Usage for Effective Memory Management -- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories -- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems -- Optimal Placement of Frequently Accessed IPs in Mesh NoCs -- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips -- Performance of Keyword Connection Algorithm in Nested Mobility Networks -- Leakage Energy Reduction in Cache Memory by Software Self-invalidation -- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters -- Runtime Performance Projection Model for Dynamic Power Management -- A Power-Aware Alternative for the Perceptron Branch Predictor -- Power Consumption and Performance Analysis of 3D NoCs -- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels -- Bipartition Architecture for Low Power JPEG Huffman Decoder -- A SWP Specification for Sequential Image Processing Algorithms -- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision -- FPGA-Accelerated Active Shape Model for Real-Time People Tracking -- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures -- Synchronization Mechanisms on Modern Multi-core Architectures -- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs -- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks -- Open Issues in MPI Implementation -- Implicit Transactional Memory in Kilo-Instruction Multiprocessors -- Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors -- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor -- Architectural Solution to Object-Oriented Programming
Dimensions
unknown
Extent
XIII, 400 p. Also available online.
File format
multiple file formats
Form of item
electronic
Isbn
9783540743095
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-540-74309-5
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-74309-5
Label
Advances in Computer Systems Architecture : 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007. Proceedings, edited by Lynn Choi, Yunheung Paek, Sangyeun Cho, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
A Compiler Framework for Supporting Speculative Multicore Processors -- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence -- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System -- Unbiased Branches: An Open Problem -- An Online Profile Guided Optimization Approach for Speculative Parallel Threading -- Entropy-Based Profile Characterization and Classification for Automatic Profile Management -- Laplace Transformation on the FT64 Stream Processor -- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation -- Evolution of NAND Flash Memory Interface -- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs -- Exploiting Single-Usage for Effective Memory Management -- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories -- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems -- Optimal Placement of Frequently Accessed IPs in Mesh NoCs -- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips -- Performance of Keyword Connection Algorithm in Nested Mobility Networks -- Leakage Energy Reduction in Cache Memory by Software Self-invalidation -- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters -- Runtime Performance Projection Model for Dynamic Power Management -- A Power-Aware Alternative for the Perceptron Branch Predictor -- Power Consumption and Performance Analysis of 3D NoCs -- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels -- Bipartition Architecture for Low Power JPEG Huffman Decoder -- A SWP Specification for Sequential Image Processing Algorithms -- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision -- FPGA-Accelerated Active Shape Model for Real-Time People Tracking -- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures -- Synchronization Mechanisms on Modern Multi-core Architectures -- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs -- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks -- Open Issues in MPI Implementation -- Implicit Transactional Memory in Kilo-Instruction Multiprocessors -- Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors -- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor -- Architectural Solution to Object-Oriented Programming
Dimensions
unknown
Extent
XIII, 400 p. Also available online.
File format
multiple file formats
Form of item
electronic
Isbn
9783540743095
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-540-74309-5
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-74309-5

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