Coverart for item
The Resource Correct hardware design and verification methods : 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings, Tiziana Margaria, Tom Melham (eds.)

Correct hardware design and verification methods : 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings, Tiziana Margaria, Tom Melham (eds.)

Label
Correct hardware design and verification methods : 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings
Title
Correct hardware design and verification methods
Title remainder
11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings
Statement of responsibility
Tiziana Margaria, Tom Melham (eds.)
Creator
Contributor
Subject
Genre
Language
eng
Member of
Cataloging source
DLC
Illustrations
illustrations
Index
index present
LC call number
TK7874.75
LC item number
.C453 2001
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2001
http://bibfra.me/vocab/lite/meetingName
CHARME 2001
Nature of contents
bibliography
http://library.link/vocab/relatedWorkOrContributorDate
1964-
http://library.link/vocab/relatedWorkOrContributorName
  • Margaria-Steffen, Tiziana
  • Melham, T. F.
http://library.link/vocab/subjectName
  • Integrated circuits
  • Integrated circuits
  • vérification algorithme
  • compilation
  • conception matériel
  • vérification matériel
  • Circuits intégrés à très grande échelle
  • Circuits intégrés
  • Integrated circuits
  • Integrated circuits
  • Hardware
  • Vormgeving
  • Circuits intégrés
  • Circuits intégrés à très grande échelle
  • Formale Methode
  • Hardwareentwurf
  • Hardwareverifikation
  • Kongress
  • Model Checking
  • Top-down-Verfahren
Label
Correct hardware design and verification methods : 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings, Tiziana Margaria, Tom Melham (eds.)
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
View from the Fringe of the Fringe (Extended Summary) / Steven D. Johnson -- Hardware Synthesis Using SAFL and Application to Processor Design / Alan Mycroft and Richard Sharp -- Applications of Hierarchical Verification in Model Checking / Robert Beers, Rajnish Ghughal and Mark Aagaard -- Pruning Techniques for the SAT-Based Bounded Model Checking Problem / Ofer Shtrichman -- Heuristics for Hierarchical Partitioning with Application to Model Checking / M. Oliver Moller and Rajeev Alur -- Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs / Dirk Beyer -- Deriving Real-Time Programs from Duration Calculus Specifications / Francois Siewe and Dang Van Hung -- Reproducing Synchronization Bugs with Model Checking / Karen Yorav, Sagi Katz and Ron Kiper -- Formally-Based Design Evaluation / Kenneth J. Turner and Ji He -- Multiclock Esterel / Gerard Berry and Ellen Sentovich -- Register Transformations with Multiple Clock Domains / Alvin R. Albrecht and Alan J. Hu -- Temporal Properties of Self-Timed Rings / Anthony Winstanley and Mark Greenstreet -- Coverability Analysis Using Symbolic Model Checking / Gil Ratzaby, Shmuel Ur and Yaron Wolfsthal -- Specifying Hardware Timing with ET-Lotos / Ji He and Kenneth J. Turner -- Formal Pipeline Design / Tiberiu Seceleanu and Juha Plosila -- Verification of Basic Block Schedules Using RTL Transformations / Rajesh Radhakrishnan, Elena Teica and Ranga Vemuri -- Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking / K. L. McMillan -- Proof Engineering in the Large: Formal Verification of Pentium 4 Floating-Point Divider / Roope Kaivola and Katherine Kohatsu -- Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques / Steve McKeever and Wayne Luk -- A Higher-Level Language for Hardware Synthesis / Richard Sharp and Alan Mycroft -- Hierarchical Verification Using an MDG-HOL Hybrid Tool / Iskander Kort, Sofiene Tahar and Paul Curzon -- Exploiting Transition Locality in Automatic Verification / Enrico Tronci, Giuseppe Della Penna and Benedetto Intrigila / [et al.] -- Efficient Debugging in a Formal Verification Environment / Fady Copty, Amitai Irron and Osnat Weissberg / [et al.] -- Using Combinatorial Optimization Methods for Quantification Scheduling / P. Chauhan, E. Clarke and S. Jha / [et al.] -- Net Reductions for LTL Model-Checking / Javier Esparza and Claus Schroter -- Formal Verification of the VAMP Floating Point Unit / Christoph Berg and Christian Jacobi -- A Specification Methodology by a Collection of Compact Properties as Applied to the Intel Itanium Processor Bus Protocol / Kanna Shimizu, David L. Dill and Ching-Tsun Chou -- The Design and Verification of a Sorter Core / Koen Claessen, Mary Sheeran and Satnam Singh -- Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems for Chip / Xiaohua Kong, Radu Negulescu and Larry Weidong Ying -- Using Abstract Specifications to Verify PowerPC Custom Memories by Symbolic Trajectory Evaluation / Jayanta Bhadra, Andrew Martin and Jacob Abraham / [et al.] -- Formal Verification of Conflict Detection Algorithms / Ricky Butler, Victor Carreno and Gilles Dowek / [et al.] -- Induction-Oriented Formal Verification in Symmetric Interconnection Networks / Eric Gascard and Laurence Pierre -- A Framework for Microprocessor Correctness Statements / Mark D. Aagaard, Byron Cook and Nancy A. Day / [et al.] -- From Operational Semantics to Denotational Semantics for Verilog / Zhu Huibiao, Jonathan P. Bowen and He Jifeng -- Efficient Verification of a Class of Linear Hybrid Automata Using Linear Programming / Li Xuandong, Pei Yu and Zhao Jianhua / [et al.]
Dimensions
24 cm.
Dimensions
unknown
Extent
xii, 482 pages
Isbn
9783540425410
Lccn
2001049453
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Specific material designation
remote
System control number
  • (OCoLC)47764389
  • (OCoLC)ocm47764389
Label
Correct hardware design and verification methods : 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001, Livingston, Scotland, UK, September 4-7, 2001 : proceedings, Tiziana Margaria, Tom Melham (eds.)
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
View from the Fringe of the Fringe (Extended Summary) / Steven D. Johnson -- Hardware Synthesis Using SAFL and Application to Processor Design / Alan Mycroft and Richard Sharp -- Applications of Hierarchical Verification in Model Checking / Robert Beers, Rajnish Ghughal and Mark Aagaard -- Pruning Techniques for the SAT-Based Bounded Model Checking Problem / Ofer Shtrichman -- Heuristics for Hierarchical Partitioning with Application to Model Checking / M. Oliver Moller and Rajeev Alur -- Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs / Dirk Beyer -- Deriving Real-Time Programs from Duration Calculus Specifications / Francois Siewe and Dang Van Hung -- Reproducing Synchronization Bugs with Model Checking / Karen Yorav, Sagi Katz and Ron Kiper -- Formally-Based Design Evaluation / Kenneth J. Turner and Ji He -- Multiclock Esterel / Gerard Berry and Ellen Sentovich -- Register Transformations with Multiple Clock Domains / Alvin R. Albrecht and Alan J. Hu -- Temporal Properties of Self-Timed Rings / Anthony Winstanley and Mark Greenstreet -- Coverability Analysis Using Symbolic Model Checking / Gil Ratzaby, Shmuel Ur and Yaron Wolfsthal -- Specifying Hardware Timing with ET-Lotos / Ji He and Kenneth J. Turner -- Formal Pipeline Design / Tiberiu Seceleanu and Juha Plosila -- Verification of Basic Block Schedules Using RTL Transformations / Rajesh Radhakrishnan, Elena Teica and Ranga Vemuri -- Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking / K. L. McMillan -- Proof Engineering in the Large: Formal Verification of Pentium 4 Floating-Point Divider / Roope Kaivola and Katherine Kohatsu -- Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques / Steve McKeever and Wayne Luk -- A Higher-Level Language for Hardware Synthesis / Richard Sharp and Alan Mycroft -- Hierarchical Verification Using an MDG-HOL Hybrid Tool / Iskander Kort, Sofiene Tahar and Paul Curzon -- Exploiting Transition Locality in Automatic Verification / Enrico Tronci, Giuseppe Della Penna and Benedetto Intrigila / [et al.] -- Efficient Debugging in a Formal Verification Environment / Fady Copty, Amitai Irron and Osnat Weissberg / [et al.] -- Using Combinatorial Optimization Methods for Quantification Scheduling / P. Chauhan, E. Clarke and S. Jha / [et al.] -- Net Reductions for LTL Model-Checking / Javier Esparza and Claus Schroter -- Formal Verification of the VAMP Floating Point Unit / Christoph Berg and Christian Jacobi -- A Specification Methodology by a Collection of Compact Properties as Applied to the Intel Itanium Processor Bus Protocol / Kanna Shimizu, David L. Dill and Ching-Tsun Chou -- The Design and Verification of a Sorter Core / Koen Claessen, Mary Sheeran and Satnam Singh -- Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems for Chip / Xiaohua Kong, Radu Negulescu and Larry Weidong Ying -- Using Abstract Specifications to Verify PowerPC Custom Memories by Symbolic Trajectory Evaluation / Jayanta Bhadra, Andrew Martin and Jacob Abraham / [et al.] -- Formal Verification of Conflict Detection Algorithms / Ricky Butler, Victor Carreno and Gilles Dowek / [et al.] -- Induction-Oriented Formal Verification in Symmetric Interconnection Networks / Eric Gascard and Laurence Pierre -- A Framework for Microprocessor Correctness Statements / Mark D. Aagaard, Byron Cook and Nancy A. Day / [et al.] -- From Operational Semantics to Denotational Semantics for Verilog / Zhu Huibiao, Jonathan P. Bowen and He Jifeng -- Efficient Verification of a Class of Linear Hybrid Automata Using Linear Programming / Li Xuandong, Pei Yu and Zhao Jianhua / [et al.]
Dimensions
24 cm.
Dimensions
unknown
Extent
xii, 482 pages
Isbn
9783540425410
Lccn
2001049453
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Specific material designation
remote
System control number
  • (OCoLC)47764389
  • (OCoLC)ocm47764389

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