The Resource Digital signal integrity : modeling and simulation with interconects and packages, Brian Young

Digital signal integrity : modeling and simulation with interconects and packages, Brian Young

Label
Digital signal integrity : modeling and simulation with interconects and packages
Title
Digital signal integrity
Title remainder
modeling and simulation with interconects and packages
Statement of responsibility
Brian Young
Creator
Subject
Language
eng
Member of
Action
committed to retain for EAST
Cataloging source
DLC
http://library.link/vocab/creatorName
Young, Brian
Illustrations
illustrations
Index
index present
LC call number
TK5102.9
LC item number
.Y68 2001
Literary form
non fiction
http://library.link/vocab/subjectName
  • Signal processing
  • Telecommunication systems
  • Signal integrity (Electronics)
  • Digitale Signalverarbeitung
  • Real-time data processing
  • Signal processing
Label
Digital signal integrity : modeling and simulation with interconects and packages, Brian Young
Instantiates
Publication
Note
Includes index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • 2
  • 77
  • 2.3.2
  • Switching Incidence
  • 77
  • 2.4
  • Discontinuities
  • 80
  • 2.4.1
  • Laplace Transform
  • 81
  • 1.1.2
  • 2.4.2
  • Capacitive Load
  • 83
  • 2.4.3
  • Series Inductance
  • 84
  • 2.4.4
  • Shunt Capacitance
  • 91
  • 2.4.5
  • Bus Width and Speed
  • Impedance Step
  • 93
  • 2.5
  • Crosstalk
  • 98
  • 2.5.1
  • Capacitive Crosstalk
  • 98
  • 2.5.2
  • Inductive Crosstalk
  • 4
  • 101
  • 2.5.3
  • Total Crosstalk
  • 103
  • 2.6
  • Topology
  • 104
  • 2.7
  • Simultaneous Switching Noise
  • 110
  • 1.1.3
  • 2.8
  • System Timing
  • 111
  • 2.8.1
  • Maximum Clock Rate
  • 112
  • 2.8.2
  • Eye Diagrams
  • 114
  • 2.8.3
  • Power Distribution
  • Skew, Jitter, and Margin
  • 119
  • 2.8.4
  • Dual Data Rate
  • 121
  • 3
  • Simultaneous Switching Noise
  • 129
  • 3.1
  • Origins of SSN
  • 5
  • 131
  • 3.1.1
  • On-Chip Switching
  • 131
  • 3.1.2
  • Off-Chip Switching
  • 135
  • 3.1.3
  • Example SPICE Simulations
  • 138
  • 1.1.4
  • 3.2
  • Effective Inductance
  • 142
  • 3.2.1
  • Computing Worst-Case L[subscript eff]s
  • 143
  • 3.3
  • Off-Chip SSN Dependencies
  • 145
  • 3.3.1
  • Topology and Loading
  • Feedback and Saturation
  • 146
  • 3.4
  • SSN-Induced Skew
  • 147
  • 3.5
  • Fast Simulation of Banks
  • 147
  • 4
  • Multiport Circuits
  • 5
  • 153
  • 4.1
  • Z- and Y-Parameters
  • 153
  • 4.2
  • S-Parameters
  • 155
  • 4.2.2
  • Circuit Calculations with S-Parameters
  • 158
  • 1
  • 1.1.5
  • 4.3
  • Multiport Conversions Between S-, Y-, and Z-Parameters
  • 159
  • 4.4
  • Normalization of S-Parameters
  • 161
  • 4.5
  • Matrix Reductions
  • 163
  • 4.5.1
  • Logic Levels and Signaling
  • Null Excitation
  • 163
  • 4.5.2
  • Common Voltage Excitation
  • 164
  • 5
  • Inductance
  • 173
  • 5.1
  • Summary of an Electromagnetic Result
  • 6
  • 174
  • 5.2
  • Definitions of Inductance
  • 176
  • 5.2.1
  • Thin Wire Definition
  • 176
  • 5.2.2
  • Field-Based Definitions
  • 180
  • 1.1.6
  • 5.2.3
  • Energy-Based Definition
  • 181
  • 5.3
  • Definition of Mutual Inductance
  • 182
  • 5.3.1
  • Thin Wire Definition
  • 182
  • 5.3.2
  • Power Dissipation
  • Field-Based Definition
  • 185
  • 5.3.3
  • Energy-Based Definition
  • 185
  • 5.3.4
  • Sign
  • 186
  • 5.4
  • Calculations with Neumann's Formula
  • 7
  • 186
  • 5.4.1
  • Calculation of External Inductance for Loops of Thin Wires
  • 187
  • 5.4.2
  • Calculation of Internal Inductance for Round Wires
  • 189
  • 5.4.3
  • Frequency Dependence of Inductance
  • 191
  • 1.2
  • 5.5
  • Definition of Partial Inductance
  • 192
  • 5.6
  • Formulas for Partial Self- and Mutual Inductance
  • 193
  • 5.6.1
  • Partial Mutual Inductance between Two Parallel Wires
  • 194
  • 5.6.2
  • Signaling Standards and Logic Families
  • Partial Self-Inductance for a Round Wire
  • 195
  • 5.6.3
  • Partial Mutual Inductance of Two Colinear Wires
  • 197
  • 5.6.4
  • Assembling Solutions
  • 197
  • 5.7
  • Circuit Symbols
  • 9
  • 199
  • 5.8
  • Modal Decomposition
  • 200
  • 5.8.1
  • Diagonalization
  • 201
  • 5.8.2
  • Circuit Theory
  • 202
  • 1.2.1
  • 5.8.3
  • Manual Implementation
  • 203
  • 5.8.4
  • Passivity
  • 204
  • 5.9
  • Nonuniqueness of Partial Inductance
  • 208
  • 5.10
  • Digital Systems and Signaling
  • Noise Margins
  • Open Loop Modeling
  • 210
  • 5.11
  • Manipulating the Reference Lead
  • 213
  • 5.12
  • Model Reduction
  • 219
  • 6
  • Capacitance
  • 12
  • 229
  • 6.1o
  • Definition of Capacitance
  • 229
  • 6.2
  • Capacitance between Several Conductors
  • 233
  • 6.3
  • Energy Definition of Capacitance
  • 237
  • 1.2.2
  • 6.4
  • Frequency Dependence
  • 238
  • 6.5
  • Circuit Equations with Capacitance
  • 239
  • 6.6
  • Modal Decomposition and Passivity
  • 241
  • 6.6.1
  • Setup and Hold Times
  • Modal Decomposition
  • 241
  • 6.6.2
  • Passivity
  • 243
  • 6.7
  • Reference and Capacitance
  • 244
  • 6.8
  • Model Reduction
  • 13
  • 245
  • 7
  • Resistance
  • 249
  • 7.1
  • Skin Effect
  • 252
  • 7.2
  • Current Crowding
  • 255
  • 1.2.3
  • 7.3
  • PEEC Method
  • 257
  • 7.3.1
  • General Formulation
  • 258
  • 7.3.2
  • Dedicated Solver
  • 260
  • 7.3.3
  • Drivers
  • In-Circuit Solution
  • 262
  • 7.3.4
  • Practical Issues
  • 263
  • 7.3.5
  • Example: PEEC Computation of Coaxial Inductance
  • 263
  • 7.4
  • Ladder Networks
  • 14
  • 264
  • 7.5
  • Transresistance
  • 270
  • 8
  • Measurement of Parasitics
  • 275
  • 8.1
  • Measurement Counts
  • 276
  • 1.2.4
  • 8.2
  • Impedance Analyzer
  • 276
  • 8.3
  • Vector Network Analyzer
  • 279
  • 8.3.1
  • Calibration
  • 282
  • 8.3.2
  • Linear Driver Modeling
  • Single Lumped Parasitic Extraction
  • 283
  • 8.3.3
  • Measurements of Multiport Networks with VNAs
  • 284
  • 8.3.4
  • Conversions between Types
  • 288
  • 8.3.5
  • Smith Chart
  • 1
  • 23
  • 289
  • 8.4
  • Time-Domain Reflectometer
  • 292
  • 8.4.1
  • Inductance Extraction
  • 293
  • 8.4.2
  • Capacitance Extraction
  • 295
  • 1.2.5
  • 8.4.3
  • Impedance Profile
  • 297
  • 8.4.4
  • Layer Peeling
  • 298
  • 8.4.5
  • Resolution
  • 305
  • 8.4.6
  • Receivers
  • Multiport TDR Measurements
  • 305
  • 8.5
  • Tradeoffs
  • 307
  • 9
  • Lumped Modeling
  • 311
  • 9.1
  • Transmission Line Introduction
  • 24
  • 312
  • 9.2
  • Multiconductor Modeling with Two Samples
  • 313
  • 9.3
  • Multiconductor Modeling with One Sample
  • 316
  • 9.3.1
  • [pi]-Network Topology
  • 317
  • 1.2.6
  • 9.3.2
  • T-Network Topology
  • 318
  • 9.3.3
  • Practical Issues
  • 319
  • 9.4
  • Internal Nodes
  • 320
  • 9.5
  • Receiver Modeling
  • Frequency Dependence
  • 324
  • 9.6
  • Iterative Impedance and Bandwidth
  • 326
  • 9.7
  • Model Reduction
  • 329
  • 9.7.1
  • Parallel Leads
  • 28
  • 329
  • 9.7.2
  • Open, Short, and Matched Leads
  • 329
  • 9.7.3
  • Excess Leads
  • 330
  • 9.7.4
  • Symmetry
  • 331
  • 1.3
  • 9.8
  • Approaches for Specific Interconnects
  • 332
  • 9.8.1
  • QFP
  • 332
  • 9.8.2
  • Edge Connectors
  • 334
  • 9.8.3
  • Interconnects
  • BGA
  • 335
  • 9.8.4
  • Internal Nodes
  • 336
  • 9.9
  • General Topology
  • 336
  • 9.10
  • Multidrop Nets
  • 28
  • 339
  • 10
  • Wideband Modeling
  • 345
  • 10.1
  • Transmission Line Lumped Modeling
  • 346
  • 10.1.1
  • Limits of Lumped Modeling
  • 346
  • 1.1
  • 1.4
  • 10.1.2
  • Multilumped Models
  • 347
  • 10.2
  • Coupled Transmission Lines
  • 348
  • 10.2.1
  • Telegrapher Equations
  • 349
  • 10.2.2
  • Modeling of Digital Systems
  • Modal Decomposition
  • 351
  • 10.2.3
  • Modal Decomposition Examples
  • 357
  • 10.3
  • Skin Effect Models
  • 368
  • 10.4
  • Black Box Modeling
  • 32
  • 369
  • 10.4.1
  • Single Port
  • 371
  • 10.4.2
  • Multiple Ports
  • 380
  • 11
  • Enhancing Signal Integrity
  • 391
  • 1.4.1
  • 11.1
  • Differential Signaling
  • 391
  • 11.2
  • Termination
  • 394
  • 11.2.1
  • Parasitics and Location
  • 394
  • 11.2.2
  • Analog Quality of Digital Waveforms
  • Static Power Dissipation and Current Carrying Requirements
  • 395
  • 11.2.3
  • Voltage Swing
  • 398
  • 11.2.4
  • Diode Termination
  • 399
  • 11.2.5
  • Source Termination
  • 40
  • 400
  • 11.3
  • Multiconductor Termination
  • 402
  • 11.3.1
  • Single Transmission Line
  • 404
  • 11.3.2
  • Differential Pair
  • 404
  • 1.4.2
  • 11.4
  • Power Distribution
  • 408
  • 11.4.1
  • Target Impedance
  • 408
  • 11.4.2
  • Design Overview
  • 409
  • 11.4.3
  • Modeling, Frequency Content, and Bandwidth
  • Capacitor Modeling
  • 414
  • 11.4.4
  • PCB Modeling
  • 415
  • 11.4.5
  • Core Noise Modeling
  • 417
  • 11.5
  • Advanced Packaging
  • 42
  • 420
  • Appendix B
  • Coaxial PEEC Calculator
  • 483
  • Appendix C
  • Sample Spice SSN Simulations
  • 493
  • Appendix D
  • Sample Modal Decomposition Code
  • 499
  • 1.4.3
  • Appendix E
  • Sample Layer Peeling Code
  • 517
  • Tradeoffs for Performance Enhancement
  • Process Variations
  • 52
  • 1.4.4
  • Challenges for Modeling High-Speed Systems
  • 53
  • 2
  • Signal Integrity
  • 55
  • 2.1
  • Transmission Lines
  • 2
  • 56
  • 2.1.1
  • Time-Domain Solution
  • 57
  • 2.1.2
  • Directional Independence
  • 60
  • 2.1.3
  • Frequency-Domain Solution
  • 62
  • 1.1.1
  • 2.1.4
  • Impedance Boundaries
  • 70
  • 2.2
  • Ideal Point-to-Point Signaling
  • 71
  • 2.2.1
  • Fast and Slow Edges
  • 73
  • 2.2.2
  • Architecture
  • Source and Parallel Termination
  • 73
  • 2.2.3
  • Source Termination Only
  • 76
  • 2.3
  • Nonideal Signaling
  • 77
  • 2.3.1
  • Synchronous vs. Asynchronous
Dimensions
25 cm
Extent
xv, 535 pages
Isbn
9780130289049
Lccn
00056676
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Other physical details
illustrations
System control number
  • (OCoLC)44469018
  • (OCoLC)ocm44469018
Label
Digital signal integrity : modeling and simulation with interconects and packages, Brian Young
Publication
Note
Includes index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • 2
  • 77
  • 2.3.2
  • Switching Incidence
  • 77
  • 2.4
  • Discontinuities
  • 80
  • 2.4.1
  • Laplace Transform
  • 81
  • 1.1.2
  • 2.4.2
  • Capacitive Load
  • 83
  • 2.4.3
  • Series Inductance
  • 84
  • 2.4.4
  • Shunt Capacitance
  • 91
  • 2.4.5
  • Bus Width and Speed
  • Impedance Step
  • 93
  • 2.5
  • Crosstalk
  • 98
  • 2.5.1
  • Capacitive Crosstalk
  • 98
  • 2.5.2
  • Inductive Crosstalk
  • 4
  • 101
  • 2.5.3
  • Total Crosstalk
  • 103
  • 2.6
  • Topology
  • 104
  • 2.7
  • Simultaneous Switching Noise
  • 110
  • 1.1.3
  • 2.8
  • System Timing
  • 111
  • 2.8.1
  • Maximum Clock Rate
  • 112
  • 2.8.2
  • Eye Diagrams
  • 114
  • 2.8.3
  • Power Distribution
  • Skew, Jitter, and Margin
  • 119
  • 2.8.4
  • Dual Data Rate
  • 121
  • 3
  • Simultaneous Switching Noise
  • 129
  • 3.1
  • Origins of SSN
  • 5
  • 131
  • 3.1.1
  • On-Chip Switching
  • 131
  • 3.1.2
  • Off-Chip Switching
  • 135
  • 3.1.3
  • Example SPICE Simulations
  • 138
  • 1.1.4
  • 3.2
  • Effective Inductance
  • 142
  • 3.2.1
  • Computing Worst-Case L[subscript eff]s
  • 143
  • 3.3
  • Off-Chip SSN Dependencies
  • 145
  • 3.3.1
  • Topology and Loading
  • Feedback and Saturation
  • 146
  • 3.4
  • SSN-Induced Skew
  • 147
  • 3.5
  • Fast Simulation of Banks
  • 147
  • 4
  • Multiport Circuits
  • 5
  • 153
  • 4.1
  • Z- and Y-Parameters
  • 153
  • 4.2
  • S-Parameters
  • 155
  • 4.2.2
  • Circuit Calculations with S-Parameters
  • 158
  • 1
  • 1.1.5
  • 4.3
  • Multiport Conversions Between S-, Y-, and Z-Parameters
  • 159
  • 4.4
  • Normalization of S-Parameters
  • 161
  • 4.5
  • Matrix Reductions
  • 163
  • 4.5.1
  • Logic Levels and Signaling
  • Null Excitation
  • 163
  • 4.5.2
  • Common Voltage Excitation
  • 164
  • 5
  • Inductance
  • 173
  • 5.1
  • Summary of an Electromagnetic Result
  • 6
  • 174
  • 5.2
  • Definitions of Inductance
  • 176
  • 5.2.1
  • Thin Wire Definition
  • 176
  • 5.2.2
  • Field-Based Definitions
  • 180
  • 1.1.6
  • 5.2.3
  • Energy-Based Definition
  • 181
  • 5.3
  • Definition of Mutual Inductance
  • 182
  • 5.3.1
  • Thin Wire Definition
  • 182
  • 5.3.2
  • Power Dissipation
  • Field-Based Definition
  • 185
  • 5.3.3
  • Energy-Based Definition
  • 185
  • 5.3.4
  • Sign
  • 186
  • 5.4
  • Calculations with Neumann's Formula
  • 7
  • 186
  • 5.4.1
  • Calculation of External Inductance for Loops of Thin Wires
  • 187
  • 5.4.2
  • Calculation of Internal Inductance for Round Wires
  • 189
  • 5.4.3
  • Frequency Dependence of Inductance
  • 191
  • 1.2
  • 5.5
  • Definition of Partial Inductance
  • 192
  • 5.6
  • Formulas for Partial Self- and Mutual Inductance
  • 193
  • 5.6.1
  • Partial Mutual Inductance between Two Parallel Wires
  • 194
  • 5.6.2
  • Signaling Standards and Logic Families
  • Partial Self-Inductance for a Round Wire
  • 195
  • 5.6.3
  • Partial Mutual Inductance of Two Colinear Wires
  • 197
  • 5.6.4
  • Assembling Solutions
  • 197
  • 5.7
  • Circuit Symbols
  • 9
  • 199
  • 5.8
  • Modal Decomposition
  • 200
  • 5.8.1
  • Diagonalization
  • 201
  • 5.8.2
  • Circuit Theory
  • 202
  • 1.2.1
  • 5.8.3
  • Manual Implementation
  • 203
  • 5.8.4
  • Passivity
  • 204
  • 5.9
  • Nonuniqueness of Partial Inductance
  • 208
  • 5.10
  • Digital Systems and Signaling
  • Noise Margins
  • Open Loop Modeling
  • 210
  • 5.11
  • Manipulating the Reference Lead
  • 213
  • 5.12
  • Model Reduction
  • 219
  • 6
  • Capacitance
  • 12
  • 229
  • 6.1o
  • Definition of Capacitance
  • 229
  • 6.2
  • Capacitance between Several Conductors
  • 233
  • 6.3
  • Energy Definition of Capacitance
  • 237
  • 1.2.2
  • 6.4
  • Frequency Dependence
  • 238
  • 6.5
  • Circuit Equations with Capacitance
  • 239
  • 6.6
  • Modal Decomposition and Passivity
  • 241
  • 6.6.1
  • Setup and Hold Times
  • Modal Decomposition
  • 241
  • 6.6.2
  • Passivity
  • 243
  • 6.7
  • Reference and Capacitance
  • 244
  • 6.8
  • Model Reduction
  • 13
  • 245
  • 7
  • Resistance
  • 249
  • 7.1
  • Skin Effect
  • 252
  • 7.2
  • Current Crowding
  • 255
  • 1.2.3
  • 7.3
  • PEEC Method
  • 257
  • 7.3.1
  • General Formulation
  • 258
  • 7.3.2
  • Dedicated Solver
  • 260
  • 7.3.3
  • Drivers
  • In-Circuit Solution
  • 262
  • 7.3.4
  • Practical Issues
  • 263
  • 7.3.5
  • Example: PEEC Computation of Coaxial Inductance
  • 263
  • 7.4
  • Ladder Networks
  • 14
  • 264
  • 7.5
  • Transresistance
  • 270
  • 8
  • Measurement of Parasitics
  • 275
  • 8.1
  • Measurement Counts
  • 276
  • 1.2.4
  • 8.2
  • Impedance Analyzer
  • 276
  • 8.3
  • Vector Network Analyzer
  • 279
  • 8.3.1
  • Calibration
  • 282
  • 8.3.2
  • Linear Driver Modeling
  • Single Lumped Parasitic Extraction
  • 283
  • 8.3.3
  • Measurements of Multiport Networks with VNAs
  • 284
  • 8.3.4
  • Conversions between Types
  • 288
  • 8.3.5
  • Smith Chart
  • 1
  • 23
  • 289
  • 8.4
  • Time-Domain Reflectometer
  • 292
  • 8.4.1
  • Inductance Extraction
  • 293
  • 8.4.2
  • Capacitance Extraction
  • 295
  • 1.2.5
  • 8.4.3
  • Impedance Profile
  • 297
  • 8.4.4
  • Layer Peeling
  • 298
  • 8.4.5
  • Resolution
  • 305
  • 8.4.6
  • Receivers
  • Multiport TDR Measurements
  • 305
  • 8.5
  • Tradeoffs
  • 307
  • 9
  • Lumped Modeling
  • 311
  • 9.1
  • Transmission Line Introduction
  • 24
  • 312
  • 9.2
  • Multiconductor Modeling with Two Samples
  • 313
  • 9.3
  • Multiconductor Modeling with One Sample
  • 316
  • 9.3.1
  • [pi]-Network Topology
  • 317
  • 1.2.6
  • 9.3.2
  • T-Network Topology
  • 318
  • 9.3.3
  • Practical Issues
  • 319
  • 9.4
  • Internal Nodes
  • 320
  • 9.5
  • Receiver Modeling
  • Frequency Dependence
  • 324
  • 9.6
  • Iterative Impedance and Bandwidth
  • 326
  • 9.7
  • Model Reduction
  • 329
  • 9.7.1
  • Parallel Leads
  • 28
  • 329
  • 9.7.2
  • Open, Short, and Matched Leads
  • 329
  • 9.7.3
  • Excess Leads
  • 330
  • 9.7.4
  • Symmetry
  • 331
  • 1.3
  • 9.8
  • Approaches for Specific Interconnects
  • 332
  • 9.8.1
  • QFP
  • 332
  • 9.8.2
  • Edge Connectors
  • 334
  • 9.8.3
  • Interconnects
  • BGA
  • 335
  • 9.8.4
  • Internal Nodes
  • 336
  • 9.9
  • General Topology
  • 336
  • 9.10
  • Multidrop Nets
  • 28
  • 339
  • 10
  • Wideband Modeling
  • 345
  • 10.1
  • Transmission Line Lumped Modeling
  • 346
  • 10.1.1
  • Limits of Lumped Modeling
  • 346
  • 1.1
  • 1.4
  • 10.1.2
  • Multilumped Models
  • 347
  • 10.2
  • Coupled Transmission Lines
  • 348
  • 10.2.1
  • Telegrapher Equations
  • 349
  • 10.2.2
  • Modeling of Digital Systems
  • Modal Decomposition
  • 351
  • 10.2.3
  • Modal Decomposition Examples
  • 357
  • 10.3
  • Skin Effect Models
  • 368
  • 10.4
  • Black Box Modeling
  • 32
  • 369
  • 10.4.1
  • Single Port
  • 371
  • 10.4.2
  • Multiple Ports
  • 380
  • 11
  • Enhancing Signal Integrity
  • 391
  • 1.4.1
  • 11.1
  • Differential Signaling
  • 391
  • 11.2
  • Termination
  • 394
  • 11.2.1
  • Parasitics and Location
  • 394
  • 11.2.2
  • Analog Quality of Digital Waveforms
  • Static Power Dissipation and Current Carrying Requirements
  • 395
  • 11.2.3
  • Voltage Swing
  • 398
  • 11.2.4
  • Diode Termination
  • 399
  • 11.2.5
  • Source Termination
  • 40
  • 400
  • 11.3
  • Multiconductor Termination
  • 402
  • 11.3.1
  • Single Transmission Line
  • 404
  • 11.3.2
  • Differential Pair
  • 404
  • 1.4.2
  • 11.4
  • Power Distribution
  • 408
  • 11.4.1
  • Target Impedance
  • 408
  • 11.4.2
  • Design Overview
  • 409
  • 11.4.3
  • Modeling, Frequency Content, and Bandwidth
  • Capacitor Modeling
  • 414
  • 11.4.4
  • PCB Modeling
  • 415
  • 11.4.5
  • Core Noise Modeling
  • 417
  • 11.5
  • Advanced Packaging
  • 42
  • 420
  • Appendix B
  • Coaxial PEEC Calculator
  • 483
  • Appendix C
  • Sample Spice SSN Simulations
  • 493
  • Appendix D
  • Sample Modal Decomposition Code
  • 499
  • 1.4.3
  • Appendix E
  • Sample Layer Peeling Code
  • 517
  • Tradeoffs for Performance Enhancement
  • Process Variations
  • 52
  • 1.4.4
  • Challenges for Modeling High-Speed Systems
  • 53
  • 2
  • Signal Integrity
  • 55
  • 2.1
  • Transmission Lines
  • 2
  • 56
  • 2.1.1
  • Time-Domain Solution
  • 57
  • 2.1.2
  • Directional Independence
  • 60
  • 2.1.3
  • Frequency-Domain Solution
  • 62
  • 1.1.1
  • 2.1.4
  • Impedance Boundaries
  • 70
  • 2.2
  • Ideal Point-to-Point Signaling
  • 71
  • 2.2.1
  • Fast and Slow Edges
  • 73
  • 2.2.2
  • Architecture
  • Source and Parallel Termination
  • 73
  • 2.2.3
  • Source Termination Only
  • 76
  • 2.3
  • Nonideal Signaling
  • 77
  • 2.3.1
  • Synchronous vs. Asynchronous
Dimensions
25 cm
Extent
xv, 535 pages
Isbn
9780130289049
Lccn
00056676
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Other physical details
illustrations
System control number
  • (OCoLC)44469018
  • (OCoLC)ocm44469018

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