The Resource FPGA-BASED Hardware Accelerators, by Iouliia Skliarova, Valery Sklyarov, (electronic resource)

FPGA-BASED Hardware Accelerators, by Iouliia Skliarova, Valery Sklyarov, (electronic resource)

Label
FPGA-BASED Hardware Accelerators
Title
FPGA-BASED Hardware Accelerators
Statement of responsibility
by Iouliia Skliarova, Valery Sklyarov
Creator
Contributor
Author
Author
Provider
Subject
Language
eng
Summary
This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design
Member of
http://library.link/vocab/creatorName
Skliarova, Iouliia
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsaut
  • 5p1_jxl3PM4
  • YI98x7LHQBg
Image bit depth
0
LC call number
TK7888.4
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Sklyarov, Valery
  • SpringerLink
Series statement
Lecture Notes in Electrical Engineering,
Series volume
566
http://library.link/vocab/subjectName
  • Systems engineering
  • Engineering
  • Circuits and Systems
  • Computational Intelligence
Label
FPGA-BASED Hardware Accelerators, by Iouliia Skliarova, Valery Sklyarov, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design
Dimensions
unknown
Extent
XVI, 245 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783030207212
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-030-20721-2
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-030-20721-2
Label
FPGA-BASED Hardware Accelerators, by Iouliia Skliarova, Valery Sklyarov, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design
Dimensions
unknown
Extent
XVI, 245 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783030207212
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-030-20721-2
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-030-20721-2

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