Coverart for item
The Resource Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping : Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers, edited by Herbert Grünbacher, Reiner W. Hartenstein, (electronic resource)

Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping : Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers, edited by Herbert Grünbacher, Reiner W. Hartenstein, (electronic resource)

Label
Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping : Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers
Title
Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping
Title remainder
Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers
Statement of responsibility
edited by Herbert Grünbacher, Reiner W. Hartenstein
Creator
Contributor
Editor
Provider
Subject
Language
eng
Summary
This book contains papers first presented at the Second International Workshop on Field-Programmable Logic and Applications (FPL '92), held in Vienna, Austria, in August-September 1992. The growing importance of field-programmable devices, especially of field-programmable gate arrays, is demonstrated by the increased number of papers submitted in 1992. Of the 70 papers submitted, 23 were selected for this book. The first three papers were invited and discuss strategic issues and give surveys. Three papers deal with new FPGA architectures and five papers introduce methods and tools. The last twelve papers report applications focusing on rapid prototyping or new FPGA-based computer architectures. The invited papersare: "Overview of complex array-based PLDs" by G. Biehl; "Technologies and utilization of field programmable gate arrays" by J. Isoaho, A. Nummela, andH. Tenhunen; and "Some considerations on field-programmable gate arrays and their impact on system design" by A. Sangiovanni-Vincentelli
Member of
http://library.link/vocab/creatorName
Grünbacher, Herbert
Image bit depth
0
LC call number
QA76.9.L63
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Hartenstein, Reiner W.
  • SpringerLink
Series statement
Lecture Notes in Computer Science,
Series volume
705
http://library.link/vocab/subjectName
  • Computer science
  • Logic design
  • Electronics
  • Computer Science
  • Logic Design
  • Electronics and Microelectronics, Instrumentation
Label
Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping : Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers, edited by Herbert Grünbacher, Reiner W. Hartenstein, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Overview of complex array-based PLDs -- Technologies and utilization of Field Programmable Gate Arrays -- Some considerations on Field Programmable Gate Arrays and their impact on system design -- SRAM-based FPGAs ease system verification -- MONTAGE: An FPGA for synchronous and asynchronous circuits -- ORCA: A new architecture for high-performance FPGAs -- Patching method for lookup-table type FPGA's -- Automatic one-hot re-encoding for FPGAs -- Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays -- Self-organizing Kohonen maps for FPGA placement -- High level synthesis in an FPGA-based computer aided prototyping environment -- New application of FPGAs to programmable digital communication circuits -- FPGA based logic synthesis of squarers using VHDL -- Optimized fuzzy controller architecture for field programmable gate arrays -- A real-time kernel — Rapid prototyping with VHDL and FPGAs -- JAPROC — A 8 bit micro controller design and its test environment -- Chameleon: A workstation of a different colour -- A highly parallel FPGA-based machine and its formal verification -- FPGA based self-test with deterministic test patterns -- FPGA implementation of systolic sequence alignment -- Using FPGAs to prototype a self-timed computer -- Using FPGAs to implement a reconfigurable highly parallel computer -- Novel high performance machine paradigms and fast-turnaround ASIC design methods: A consequence of, and, a challenge to, field-programmable logic
Dimensions
unknown
Extent
IX, 223 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783540479024
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/3-540-57091-8
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-47902-4
Label
Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping : Second International Workshop on Field-Programmable Logic and Applications Vienna, Austria, August 31 – September 2, 1992 Selected Papers, edited by Herbert Grünbacher, Reiner W. Hartenstein, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Overview of complex array-based PLDs -- Technologies and utilization of Field Programmable Gate Arrays -- Some considerations on Field Programmable Gate Arrays and their impact on system design -- SRAM-based FPGAs ease system verification -- MONTAGE: An FPGA for synchronous and asynchronous circuits -- ORCA: A new architecture for high-performance FPGAs -- Patching method for lookup-table type FPGA's -- Automatic one-hot re-encoding for FPGAs -- Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays -- Self-organizing Kohonen maps for FPGA placement -- High level synthesis in an FPGA-based computer aided prototyping environment -- New application of FPGAs to programmable digital communication circuits -- FPGA based logic synthesis of squarers using VHDL -- Optimized fuzzy controller architecture for field programmable gate arrays -- A real-time kernel — Rapid prototyping with VHDL and FPGAs -- JAPROC — A 8 bit micro controller design and its test environment -- Chameleon: A workstation of a different colour -- A highly parallel FPGA-based machine and its formal verification -- FPGA based self-test with deterministic test patterns -- FPGA implementation of systolic sequence alignment -- Using FPGAs to prototype a self-timed computer -- Using FPGAs to implement a reconfigurable highly parallel computer -- Novel high performance machine paradigms and fast-turnaround ASIC design methods: A consequence of, and, a challenge to, field-programmable logic
Dimensions
unknown
Extent
IX, 223 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783540479024
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/3-540-57091-8
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-47902-4

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