Coverart for item
The Resource Formal Methods in Computer-Aided Design : 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings, edited by Mark D. Aagaard, John W. O’Leary, (electronic resource)

Formal Methods in Computer-Aided Design : 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings, edited by Mark D. Aagaard, John W. O’Leary, (electronic resource)

Label
Formal Methods in Computer-Aided Design : 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings
Title
Formal Methods in Computer-Aided Design
Title remainder
4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings
Statement of responsibility
edited by Mark D. Aagaard, John W. O’Leary
Creator
Contributor
Editor
Provider
Subject
Language
eng
Summary
This book constitutes the refereed proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2002, held in Portland, OR, USA in November 2002. The 23 revised full papers presented were carefully reviewed and selected from 47 submissions. The book offers topial sections on abstraction, symbolic simulation, model checking, microprocessor specification and verification, decision procedures, verification techniques and methodology, hardware description languages, and prototyping and synthesis
Member of
http://library.link/vocab/creatorName
Aagaard, Mark D
Image bit depth
0
LC call number
  • QA75.5-76.95
  • TK7885-7895
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • O’Leary, John W.
  • SpringerLink
Series statement
Lecture Notes in Computer Science,
Series volume
2517
http://library.link/vocab/subjectName
  • Computer science
  • Computer hardware
  • Software engineering
  • Logic design
  • Computer Science
  • Computer Hardware
  • Software Engineering
  • Logics and Meanings of Programs
  • Mathematical Logic and Formal Languages
  • Electronic and Computer Engineering
Label
Formal Methods in Computer-Aided Design : 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings, edited by Mark D. Aagaard, John W. O’Leary, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Abstraction -- Abstraction by Symbolic Indexing Transformations -- Counter-Example Based Predicate Discovery in Predicate Abstraction -- Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis -- Symbolic Simulation -- Simplifying Circuits for Formal Verification Using Parametric Representation -- Generalized Symbolic Trajectory Evaluation — Abstraction in Action -- Model Checking: Strongly-Connected Components -- Analysis of Symbolic SCC Hull Algorithms -- Sharp Disjunctive Decomposition for Language Emptiness Checking -- Microprocessor Specification and Verification -- Relating Multi-step and Single-Step Microprocessor Correctness Statements -- Modeling and Verification of Out-of-Order Microprocessors in UCLID -- Decision Procedures -- On Solving Presburger and Linear Arithmetic with SAT -- Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods -- Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers -- Model Checking: Reachability Analysis -- Exploiting Transition Locality in the Disk Based Mur? Verifier -- Traversal Techniques for Concurrent Systems -- Model Checking: Fixed Points -- A Fixpoint Based Encoding for Bounded Model Checking -- Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths -- Verification Techniques and Methodology -- Mechanical Verification of a Square Root Algorithm Using Taylor’s Theorem -- A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols -- Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV -- Hardware Description Languages -- Functional Design Using Behavioural and Structural Components -- Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries -- Prototyping and Synthesis -- Input/Output Compatibility of Reactive Systems -- Smart Play-out of Behavioral Requirements
Dimensions
unknown
Extent
XII, 408 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783540361268
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/3-540-36126-X
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-36126-8
Label
Formal Methods in Computer-Aided Design : 4th International Conference, FMCAD 2002 Portland, OR, USA, November 6–8, 2002 Proceedings, edited by Mark D. Aagaard, John W. O’Leary, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Abstraction -- Abstraction by Symbolic Indexing Transformations -- Counter-Example Based Predicate Discovery in Predicate Abstraction -- Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis -- Symbolic Simulation -- Simplifying Circuits for Formal Verification Using Parametric Representation -- Generalized Symbolic Trajectory Evaluation — Abstraction in Action -- Model Checking: Strongly-Connected Components -- Analysis of Symbolic SCC Hull Algorithms -- Sharp Disjunctive Decomposition for Language Emptiness Checking -- Microprocessor Specification and Verification -- Relating Multi-step and Single-Step Microprocessor Correctness Statements -- Modeling and Verification of Out-of-Order Microprocessors in UCLID -- Decision Procedures -- On Solving Presburger and Linear Arithmetic with SAT -- Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods -- Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers -- Model Checking: Reachability Analysis -- Exploiting Transition Locality in the Disk Based Mur? Verifier -- Traversal Techniques for Concurrent Systems -- Model Checking: Fixed Points -- A Fixpoint Based Encoding for Bounded Model Checking -- Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths -- Verification Techniques and Methodology -- Mechanical Verification of a Square Root Algorithm Using Taylor’s Theorem -- A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols -- Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV -- Hardware Description Languages -- Functional Design Using Behavioural and Structural Components -- Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries -- Prototyping and Synthesis -- Input/Output Compatibility of Reactive Systems -- Smart Play-out of Behavioral Requirements
Dimensions
unknown
Extent
XII, 408 p.
File format
multiple file formats
Form of item
electronic
Isbn
9783540361268
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/3-540-36126-X
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-36126-8

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