The Resource Formal Verification of Floating-Point Hardware Design : A Mathematical Approach, by David M. Russinoff, (electronic resource)

Formal Verification of Floating-Point Hardware Design : A Mathematical Approach, by David M. Russinoff, (electronic resource)

Label
Formal Verification of Floating-Point Hardware Design : A Mathematical Approach
Title
Formal Verification of Floating-Point Hardware Design
Title remainder
A Mathematical Approach
Statement of responsibility
by David M. Russinoff
Creator
Contributor
Author
Author
Provider
Subject
Language
eng
Summary
This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The book consists of five parts, the first two of which present a rigorous exposition of the general theory based on the first principles of arithmetic. Part I covers bit vectors and the bit manipulation primitives, integer and fixed-point encodings, and bit-wise logical operations. Part II addresses the properties of floating-point numbers, the formats in which they are encoded as bit vectors, and the various modes of floating-point rounding. In Part III, the theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, Part IV contains high-level specifications of correctness of the basic arithmetic instructions of several major industry-standard floating-point architectures, including all details pertaining to the handling of exceptional conditions. Part V illustrates the methodology, applying the preceding theory to the comprehensive verification of a state-of-the-art commercial floating-point unit. All of these results have been formalized in the logic of the ACL2 theorem prover and mechanically checked to ensure their correctness. They are presented here, however, in simple conventional mathematical notation. The book presupposes no familiarity with ACL2, logic design, or any mathematics beyond basic high school algebra. It will be of interest to verification engineers as well as arithmetic circuit designers who appreciate the value of a rigorous approach to their art, and is suitable as a graduate text in computer arithmetic.
http://library.link/vocab/creatorName
Russinoff, David M
http://bibfra.me/vocab/relation/httpidlocgovvocabularyrelatorsaut
lNjD3GiLLA8
Image bit depth
0
LC call number
TK7888.4
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
SpringerLink
http://library.link/vocab/subjectName
  • Systems engineering
  • Software engineering
  • Computer science
  • Operating systems (Computers)
  • Circuits and Systems
  • Software Engineering
  • Processor Architectures
  • Performance and Reliability
Label
Formal Verification of Floating-Point Hardware Design : A Mathematical Approach, by David M. Russinoff, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
1 Basic Arithmetic Functions -- 2 Bit Vectors -- 3 Logical Operations -- 4 Floating-Point Numbers -- 5 Floating-Point Formats -- 6 Rounding -- 7 IEEE-Compliant Square Root -- 8 Addition -- 9 Multiplication -- 10 SRT Division and Square Root -- 11 FMA-Based Division -- 12 SSE Floating-Point Instructions -- 13 x87 Instructions -- 14 Arm Floating-Point Instructions -- 15 The Modeling Language -- 16 Double-Precision Multiplication -- 17 Double-Precision Addition and FMA -- 18 Multi-Precision Radix-4 SRT Division -- 19 Multi-Precision Radix-4 SRT Square Root
Dimensions
unknown
Extent
XXIV, 382 p. 32 illus.
File format
multiple file formats
Form of item
electronic
Isbn
9783319955131
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-319-95513-1
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-319-95513-1
Label
Formal Verification of Floating-Point Hardware Design : A Mathematical Approach, by David M. Russinoff, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
1 Basic Arithmetic Functions -- 2 Bit Vectors -- 3 Logical Operations -- 4 Floating-Point Numbers -- 5 Floating-Point Formats -- 6 Rounding -- 7 IEEE-Compliant Square Root -- 8 Addition -- 9 Multiplication -- 10 SRT Division and Square Root -- 11 FMA-Based Division -- 12 SSE Floating-Point Instructions -- 13 x87 Instructions -- 14 Arm Floating-Point Instructions -- 15 The Modeling Language -- 16 Double-Precision Multiplication -- 17 Double-Precision Addition and FMA -- 18 Multi-Precision Radix-4 SRT Division -- 19 Multi-Precision Radix-4 SRT Square Root
Dimensions
unknown
Extent
XXIV, 382 p. 32 illus.
File format
multiple file formats
Form of item
electronic
Isbn
9783319955131
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-319-95513-1
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-319-95513-1

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