Coverart for item
The Resource Hardware Description Languages and their Applications : Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain, edited by Carlos Delgado Kloos, Eduard Cerny, (electronic resource)

Hardware Description Languages and their Applications : Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain, edited by Carlos Delgado Kloos, Eduard Cerny, (electronic resource)

Label
Hardware Description Languages and their Applications : Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain
Title
Hardware Description Languages and their Applications
Title remainder
Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain
Statement of responsibility
edited by Carlos Delgado Kloos, Eduard Cerny
Creator
Contributor
Editor
Provider
Subject
Language
eng
Summary
In the past few decades Computer Hardware Description Languages (CHDLs) have been a rapidly expanding subject area due to a number of factors, including the advancing complexity of digital electronics, the increasing prevalence of generic and programmable components of software-hardware and the migration of VLSI design to high level synthesis based on HDLs. Currently the subject has reached the consolidation phase in which languages and standards are being increasingly used, at the same time as the scope is being broadened to additional application areas. This book presents the latest developments in this area and provides a forum from which readers can learn from the past and look forward to what the future holds
Member of
http://library.link/vocab/creatorName
Kloos, Carlos Delgado
Image bit depth
0
LC call number
  • QA76.7-76.73
  • QA76.76.C65
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Cerny, Eduard.
  • SpringerLink
Series statement
IFIP — The International Federation for Information Processing,
http://library.link/vocab/subjectName
  • Computer science
  • Machinery
  • Computer Science
  • Programming Languages, Compilers, Interpreters
  • Manufacturing, Machines, Tools
Label
Hardware Description Languages and their Applications : Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain, edited by Carlos Delgado Kloos, Eduard Cerny, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
1 Synchronous languages for hardware and software reactive systems -- 2 Towards a complete design method for embedded systems using Predicate/Transition-Nets -- 3 Simplifying data operations for formal verification -- 4 CTL and equivalent sublanguages of CTL -- 5 Verifying linear temporal properties of data intensive controllers using finite instantiations -- 6 A high-level language for programming complex temporal behaviors and its translation into synchronous circuits (poster abstract) -- 7 System-level hardware design with ?-charts (poster abstract) -- 8 Interface synthesis in embedded hardware-software systems (poster abstract) -- 9 TripleS-a formal validation environment for functional specifications (poster abstract) -- 10 SOFHIA: a CAD environment to design digital control systems (poster abstract) -- 11 Compiling the language BALSA to delay insensitive hardware (poster abstract) -- 12 High-level synthesis of structured data paths (poster abstract) -- 13 Characterizing a portable subset of behavioural VHDL-93 -- 14 Algebra of communicating timing charts for describing and verifying hardware interfaces -- 15 A formal proof of absence of deadlock for any acyclic network of PCI buses -- 16 Behavioural modelling of sampled-data with HDL-A and ABSynth -- 17 Hardware description languages in practical design flows -- 18 VHDL generation from SDL specification -- 19 Exploiting isomorphism for speeding up instance-binding in an integrated scheduling allocation and assignment approach to architectural synthesis -- 20 Verification of large systems in silicon (special talk) -- 21 The Shall Design test Development model for hardware systems -- 22 Modular operational semantic specification of transport triggered architectures -- 23 The world of I/O: a rich application area for formal methods (invited talk) -- 24 Abstract modelling of asynchronous micropipeline systems using Rainbow -- 25 A new partial order reduction algorithm for concurrent system verification (short talk) -- 26 VHDL power simulator: power analysis at gate level -- 27 Object oriented extensions to VHDL. the LaMI proposal -- Index of contributors -- Keyword index
Dimensions
unknown
Extent
X, 350 p.
File format
multiple file formats
Form of item
electronic
Isbn
9780387350646
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/978-0-387-35064-6
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-0-387-35064-6
Label
Hardware Description Languages and their Applications : Specification, modelling, verification and synthesis of microelectronic systems IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20–25 April 1997, Toledo, Spain, edited by Carlos Delgado Kloos, Eduard Cerny, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
1 Synchronous languages for hardware and software reactive systems -- 2 Towards a complete design method for embedded systems using Predicate/Transition-Nets -- 3 Simplifying data operations for formal verification -- 4 CTL and equivalent sublanguages of CTL -- 5 Verifying linear temporal properties of data intensive controllers using finite instantiations -- 6 A high-level language for programming complex temporal behaviors and its translation into synchronous circuits (poster abstract) -- 7 System-level hardware design with ?-charts (poster abstract) -- 8 Interface synthesis in embedded hardware-software systems (poster abstract) -- 9 TripleS-a formal validation environment for functional specifications (poster abstract) -- 10 SOFHIA: a CAD environment to design digital control systems (poster abstract) -- 11 Compiling the language BALSA to delay insensitive hardware (poster abstract) -- 12 High-level synthesis of structured data paths (poster abstract) -- 13 Characterizing a portable subset of behavioural VHDL-93 -- 14 Algebra of communicating timing charts for describing and verifying hardware interfaces -- 15 A formal proof of absence of deadlock for any acyclic network of PCI buses -- 16 Behavioural modelling of sampled-data with HDL-A and ABSynth -- 17 Hardware description languages in practical design flows -- 18 VHDL generation from SDL specification -- 19 Exploiting isomorphism for speeding up instance-binding in an integrated scheduling allocation and assignment approach to architectural synthesis -- 20 Verification of large systems in silicon (special talk) -- 21 The Shall Design test Development model for hardware systems -- 22 Modular operational semantic specification of transport triggered architectures -- 23 The world of I/O: a rich application area for formal methods (invited talk) -- 24 Abstract modelling of asynchronous micropipeline systems using Rainbow -- 25 A new partial order reduction algorithm for concurrent system verification (short talk) -- 26 VHDL power simulator: power analysis at gate level -- 27 Object oriented extensions to VHDL. the LaMI proposal -- Index of contributors -- Keyword index
Dimensions
unknown
Extent
X, 350 p.
File format
multiple file formats
Form of item
electronic
Isbn
9780387350646
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/978-0-387-35064-6
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-0-387-35064-6

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