Coverart for item
The Resource High Performance Embedded Architectures and Compilers : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings, edited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer, (electronic resource)

High Performance Embedded Architectures and Compilers : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings, edited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer, (electronic resource)

Label
High Performance Embedded Architectures and Compilers : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings
Title
High Performance Embedded Architectures and Compilers
Title remainder
Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings
Statement of responsibility
edited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer
Creator
Contributor
Editor
Provider
Subject
Language
eng
Summary
This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007. The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems
Member of
http://library.link/vocab/creatorName
Bosschere, Koen
Image bit depth
0
LC call number
QA76.9.C62
Literary form
non fiction
http://library.link/vocab/relatedWorkOrContributorName
  • Kaeli, David.
  • Stenström, Per.
  • Whalley, David.
  • Ungerer, Theo.
  • SpringerLink
Series statement
Lecture Notes in Computer Science,
Series volume
4367
http://library.link/vocab/subjectName
  • Computer science
  • Data transmission systems
  • Logic design
  • Computer Communication Networks
  • Computer Science
  • Arithmetic and Logic Structures
  • Processor Architectures
  • Input/Output and Data Communications
  • Logic Design
  • Computer Communication Networks
  • Programming Languages, Compilers, Interpreters
Label
High Performance Embedded Architectures and Compilers : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings, edited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer, (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints
Dimensions
unknown
Extent
XI, 307 p. Also available online.
File format
multiple file formats
Form of item
electronic
Isbn
9783540693383
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-540-69338-3
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-69338-3
Label
High Performance Embedded Architectures and Compilers : Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings, edited by Koen Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer, (electronic resource)
Publication
Antecedent source
mixed
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints
Dimensions
unknown
Extent
XI, 307 p. Also available online.
File format
multiple file formats
Form of item
electronic
Isbn
9783540693383
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
10.1007/978-3-540-69338-3
Other physical details
online resource.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
(DE-He213)978-3-540-69338-3

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