Coverart for item
The Resource High performance embedded architectures and compilers : 5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings, Yale N. Patt ... [et al.] (eds.), (electronic resource)

High performance embedded architectures and compilers : 5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings, Yale N. Patt ... [et al.] (eds.), (electronic resource)

Label
High performance embedded architectures and compilers : 5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings
Title
High performance embedded architectures and compilers
Title remainder
5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings
Statement of responsibility
Yale N. Patt ... [et al.] (eds.)
Title variation
HiPEAC 2010
Creator
Contributor
Provider
Subject
Genre
Language
eng
Summary
This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators
Member of
Cataloging source
CUS
Image bit depth
0
LC call number
TK7895.E42
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2010
http://bibfra.me/vocab/lite/meetingName
HiPEAC 2010
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
  • SpringerLink
  • Patt, Yale N
Series statement
Lecture Notes in Computer Science,
Series volume
5952
http://library.link/vocab/subjectName
  • Computer Systems
  • Software
  • Embedded computer systems
  • Compilers (Computer programs)
  • Computer architecture
  • Compilers (Computer programs)
  • Computer architecture
  • Embedded computer systems
  • Informatique
Label
High performance embedded architectures and compilers : 5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings, Yale N. Patt ... [et al.] (eds.), (electronic resource)
Instantiates
Publication
Note
Title from PDF t.p. (SpringerLink, viewed Jan. 27, 2010)
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Color
not applicable
Contents
Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders
Dimensions
unknown
Extent
1 online resource (xiii, 370 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9783642115158
Level of compression
uncompressed
Other physical details
ill.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
Stock number
978-3-642-11514-1
System control number
  • (OCoLC)502157199
  • (OCoLC)ocn502157199
Label
High performance embedded architectures and compilers : 5th international conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010 : proceedings, Yale N. Patt ... [et al.] (eds.), (electronic resource)
Publication
Note
Title from PDF t.p. (SpringerLink, viewed Jan. 27, 2010)
Antecedent source
mixed
Bibliography note
Includes bibliographical references and index
Color
not applicable
Contents
Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders
Dimensions
unknown
Extent
1 online resource (xiii, 370 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9783642115158
Level of compression
uncompressed
Other physical details
ill.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
Stock number
978-3-642-11514-1
System control number
  • (OCoLC)502157199
  • (OCoLC)ocn502157199

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