Coverart for item
The Resource Reconfigurable computing : architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, Oliver C. S. Choy...[et al.] (eds.), (electronic resource)

Reconfigurable computing : architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, Oliver C. S. Choy...[et al.] (eds.), (electronic resource)

Label
Reconfigurable computing : architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings
Title
Reconfigurable computing
Title remainder
architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings
Statement of responsibility
Oliver C. S. Choy...[et al.] (eds.)
Title variation
ARC 2012
Creator
Contributor
Provider
Subject
Genre
Language
eng
Summary
This book constitutes the refereed proceedings of the 8th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2012, held in Hongkong, China, in March 2012. The 35 revised papers presented, consisting of 25 full papers and 10 poster papers were carefully reviewed and selected from 44 submissions. The topics covered are applied RC design methods and tools, applied RC architectures, applied RC applications and critical issues in applied RC
Member of
Cataloging source
GW5XE
Image bit depth
0
LC call number
QA76.9.A3
LC item number
A73 2012
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2012
http://bibfra.me/vocab/lite/meetingName
ARC (Symposium)
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
  • SpringerLink
  • Choy, Oliver C. S
Series statement
Lecture Notes in Computer Science,
Series volume
7199
http://library.link/vocab/subjectName
  • Adaptive computing systems
  • Computer architecture
  • Adaptive computing systems
  • Computer architecture
  • Informatique
Label
Reconfigurable computing : architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, Oliver C. S. Choy...[et al.] (eds.), (electronic resource)
Instantiates
Publication
Note
International conference proceedings
Antecedent source
mixed
Bibliography note
Includes bibliographical references and author index
Color
not applicable
Contents
  • Table-Based Division by Small Integer Constants
  • Florent de Dinechin and Laurent-Stéphane Didier
  • Heterogeneous Systems for Energy Efficient Scientific Computing
  • Qiang Liu and Wayne Luk
  • The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
  • S. Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi and Koen Bertels
  • PPMC: A Programmable Pattern Based Memory Controller
  • Tassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé
  • A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor
  • Fakhar Anjam, Quan Kong, Roel Seedorf and Stephan Wong
  • Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration
  • Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration
  • Geoffrey Ndu and Jim Garside
  • Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs
  • Gang Zhou, Li Li and Harald Michalik
  • Karel Heyse, Brahim Al Farisi, Karel Bruneel and Dirk Stroobandt
  • Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
  • Kizheppatt Vipin and Suhaib A. Fahmy
  • Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array
  • Wang Luzhou, Kentaro Sano and Satoru Yamamoto
  • Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture
  • Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai and Ingoo Heo, et al.
  • Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations
  • Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary C. T. Chow and David B. Thomas, et al.
  • A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU
  • Hiroki Nakahara, Tsutomu Sasao and Munehiro Matsuura
  • Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration
  • Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
  • Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware
  • Grigorios Mingas and Christos-Savvas Bouganis
  • A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
  • Abid Rafique, Nachiket Kapre and George A. Constantinides
  • ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs
  • Optimising Performance of Quadrature Methods with Reduced Precision
  • Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas and Wayne Luk
  • Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform
  • Markus Weinhardt
  • Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda and Kenji Kise
  • Scalable Memory Hierarchies for Embedded Manycore Systems
  • Sen Ma, Miaoqing Huang, Eugene Cartwright and David Andrews
  • Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays
  • Takahiro Watanabe and Minoru Watanabe
  • A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters
  • Wei Ting Loke and Yajun Ha
  • Constructing Cluster of Simple FPGA Boards for Cryptologic Computations
  • Yarkin Doröz and Erkay Savaş
  • Reconfigurable Multicore Architecture for Dynamic Processor Reallocation
  • Annie Avakian, Natwar Agrawal and Ranga Vemuri
  • Efficient Communication for FPGA Clusters
  • Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch and Wayne Luk
  • Performance Analysis of Reconfigurable Processors Using MVA Analysis
  • Ehsan Zadkhosh, Sepide Fatahi and Mahmood Ahmadi
  • PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang and Jinian Bian
  • Securely Sealing Multi-FPGA Systems
  • A Connection Router for the Dynamic Reconfiguration of FPGAs
  • Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt
  • R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip
  • Hongbing Fan, Yue-Ang Chen and Yu-Liang Wu
  • Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms
  • Kashif Latif, M. Muzaffar Rao, Athar Mahboob and Arshad Aziz
  • CRAIS: A Crossbar Based Adaptive Interconnection Scheme
  • Chao Wang, Xi Li, Xuehai Zhou and Xiaojing Feng
  • Tim Güneysu, Igor Markov and André Weimerskirch
  • FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores
  • Xuan You Tan, David Boland and George Constantinides
  • High Performance Reconfigurable Architecture for Double Precision Floating Point Division
  • Manish Kumar Jaiswal and Ray C. C. Cheung
  • A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems
  • Tannous Frangieh, Richard Stroop, Peter Athanas and Teresa Cervero
Dimensions
unknown
Extent
1 online resource (xiv, 386 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9783642283659
Level of compression
uncompressed
Other control number
10.1007/978-3-642-28365-9
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (OCoLC)782910895
  • (OCoLC)ocn782910895
Label
Reconfigurable computing : architectures, tools and applications : 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, Oliver C. S. Choy...[et al.] (eds.), (electronic resource)
Publication
Note
International conference proceedings
Antecedent source
mixed
Bibliography note
Includes bibliographical references and author index
Color
not applicable
Contents
  • Table-Based Division by Small Integer Constants
  • Florent de Dinechin and Laurent-Stéphane Didier
  • Heterogeneous Systems for Energy Efficient Scientific Computing
  • Qiang Liu and Wayne Luk
  • The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
  • S. Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi and Koen Bertels
  • PPMC: A Programmable Pattern Based Memory Controller
  • Tassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé
  • A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor
  • Fakhar Anjam, Quan Kong, Roel Seedorf and Stephan Wong
  • Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration
  • Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration
  • Geoffrey Ndu and Jim Garside
  • Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs
  • Gang Zhou, Li Li and Harald Michalik
  • Karel Heyse, Brahim Al Farisi, Karel Bruneel and Dirk Stroobandt
  • Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
  • Kizheppatt Vipin and Suhaib A. Fahmy
  • Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array
  • Wang Luzhou, Kentaro Sano and Satoru Yamamoto
  • Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture
  • Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai and Ingoo Heo, et al.
  • Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations
  • Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary C. T. Chow and David B. Thomas, et al.
  • A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU
  • Hiroki Nakahara, Tsutomu Sasao and Munehiro Matsuura
  • Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration
  • Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
  • Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware
  • Grigorios Mingas and Christos-Savvas Bouganis
  • A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
  • Abid Rafique, Nachiket Kapre and George A. Constantinides
  • ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs
  • Optimising Performance of Quadrature Methods with Reduced Precision
  • Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas and Wayne Luk
  • Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform
  • Markus Weinhardt
  • Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda and Kenji Kise
  • Scalable Memory Hierarchies for Embedded Manycore Systems
  • Sen Ma, Miaoqing Huang, Eugene Cartwright and David Andrews
  • Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays
  • Takahiro Watanabe and Minoru Watanabe
  • A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters
  • Wei Ting Loke and Yajun Ha
  • Constructing Cluster of Simple FPGA Boards for Cryptologic Computations
  • Yarkin Doröz and Erkay Savaş
  • Reconfigurable Multicore Architecture for Dynamic Processor Reallocation
  • Annie Avakian, Natwar Agrawal and Ranga Vemuri
  • Efficient Communication for FPGA Clusters
  • Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch and Wayne Luk
  • Performance Analysis of Reconfigurable Processors Using MVA Analysis
  • Ehsan Zadkhosh, Sepide Fatahi and Mahmood Ahmadi
  • PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang and Jinian Bian
  • Securely Sealing Multi-FPGA Systems
  • A Connection Router for the Dynamic Reconfiguration of FPGAs
  • Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt
  • R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip
  • Hongbing Fan, Yue-Ang Chen and Yu-Liang Wu
  • Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms
  • Kashif Latif, M. Muzaffar Rao, Athar Mahboob and Arshad Aziz
  • CRAIS: A Crossbar Based Adaptive Interconnection Scheme
  • Chao Wang, Xi Li, Xuehai Zhou and Xiaojing Feng
  • Tim Güneysu, Igor Markov and André Weimerskirch
  • FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores
  • Xuan You Tan, David Boland and George Constantinides
  • High Performance Reconfigurable Architecture for Double Precision Floating Point Division
  • Manish Kumar Jaiswal and Ray C. C. Cheung
  • A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems
  • Tannous Frangieh, Richard Stroop, Peter Athanas and Teresa Cervero
Dimensions
unknown
Extent
1 online resource (xiv, 386 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9783642283659
Level of compression
uncompressed
Other control number
10.1007/978-3-642-28365-9
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
System control number
  • (OCoLC)782910895
  • (OCoLC)ocn782910895

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