Coverart for item
The Resource VLSI-SOC, from systems to chips : IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, edited by Manfred Glesner ... [et al.], (electronic resource)

VLSI-SOC, from systems to chips : IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, edited by Manfred Glesner ... [et al.], (electronic resource)

Label
VLSI-SOC, from systems to chips : IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Title
VLSI-SOC, from systems to chips
Title remainder
IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany
Statement of responsibility
edited by Manfred Glesner ... [et al.]
Creator
Contributor
Provider
Subject
Genre
Language
eng
Summary
International Federation for Information Processing The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of referred international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing. For more information about the 300 other books in the IFIP series, please visit www.springeronline.com. For more information about IFIP, please visit www.ifip.org
Member of
Cataloging source
GW5XE
Image bit depth
0
LC call number
TK7874.75
LC item number
.I25 2003eb
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2003
http://bibfra.me/vocab/lite/meetingName
IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration
Nature of contents
dictionaries
http://library.link/vocab/relatedWorkOrContributorName
  • SpringerLink
  • Glesner, Manfred
Series statement
IFIP International Federation for Information Processing,
Series volume
200
http://library.link/vocab/subjectName
  • Integrated circuits
  • Systems on a chip
  • TECHNOLOGY & ENGINEERING
  • TECHNOLOGY & ENGINEERING
  • COMPUTERS
  • Integrated circuits
  • Systems on a chip
  • Informatique
  • Electronic books
  • Integrated circuits
  • Systems on a chip
Label
VLSI-SOC, from systems to chips : IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, edited by Manfred Glesner ... [et al.], (electronic resource)
Instantiates
Publication
Antecedent source
mixed
Bibliography note
Includes bibliographical references and author index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Effect of Power Optimizations on Soft Error Rate -- Dynamic Models for Substrate Coupling in Mixed-Mode Systems -- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs -- Automated Conversion of SystemC Fixed-Point Data Types -- Exploration of Sequential Depth by Evolutionary Algorithms -- Validation of Asynchronous Circuit Specifications Using IF/CADP -- On-Chip Property Verification Using Assertion Processors -- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems -- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications -- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans -- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures -- Optimizing SOC Test Resources Using Dual Sequences -- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits -- Low Power Java Processor for Embedded Applications -- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes -- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates -- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath -- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths -- Stuck-At-Fault Testability of SPP Three-Level Logic Forms
Dimensions
unknown
Extent
1 online resource (x, 313 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9781280611186
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
ill.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
Stock number
978-0-387-33402-8
System control number
  • (OCoLC)209923888
  • (OCoLC)ocn209923888
Label
VLSI-SOC, from systems to chips : IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, edited by Manfred Glesner ... [et al.], (electronic resource)
Publication
Antecedent source
mixed
Bibliography note
Includes bibliographical references and author index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
not applicable
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Effect of Power Optimizations on Soft Error Rate -- Dynamic Models for Substrate Coupling in Mixed-Mode Systems -- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs -- Automated Conversion of SystemC Fixed-Point Data Types -- Exploration of Sequential Depth by Evolutionary Algorithms -- Validation of Asynchronous Circuit Specifications Using IF/CADP -- On-Chip Property Verification Using Assertion Processors -- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems -- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications -- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans -- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures -- Optimizing SOC Test Resources Using Dual Sequences -- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits -- Low Power Java Processor for Embedded Applications -- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes -- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates -- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath -- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths -- Stuck-At-Fault Testability of SPP Three-Level Logic Forms
Dimensions
unknown
Extent
1 online resource (x, 313 p.)
File format
multiple file formats
Form of item
  • online
  • electronic
Isbn
9781280611186
Level of compression
uncompressed
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
ill.
Quality assurance targets
absent
Reformatting quality
access
Specific material designation
remote
Stock number
978-0-387-33402-8
System control number
  • (OCoLC)209923888
  • (OCoLC)ocn209923888

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